1. Field of the Invention
The present invention relates to decoder/driver circuits for semiconductor memories, and more particularly to a circuit that can be used as a word-line decoder/driver or a bit-line decoder driver in a CMOS random access memory.
2. Description of the Prior Art
A variety of decoder circuits for semiconductor memories are available in the art.
In U.S. Pat. No. 4,309,629 issued Jan. 5, 1982 to Kamuro, entitled MOS TRANSISTOR DECODER CIRCUIT, an MOS transistor decoder circuit is disclosed including a plurality of MOS transistors and at least one load element. At least one additional MOS transistor connected to the plurality of MOS transistors and the load element for selecting either of two output terminals for the plurality of MOS transistors, through which decoded output signals are developed. The two additional MOS transistors connected to the two output terminals have normal and complement bit signals, respectively.
In U.S. Pat. No. 4,264,828 issued Apr. 28, 1981 to Perlegos et al, entitled MOS STATIC DECODING CIRCUIT, a metal-oxide-semiconductor static decoding circuit for selecting an addressed line in a high density memory array, or the like, is disclosed. The circuit is laid-out along array lines where the lines have a given pitch. Three levels of decoding are employed. The highest level permits the pulling-up of a common node in the second level decoder. The third level of decoding selects one of a plurality of array lines coupled to this node. Zero threshold voltage MOS devices are employed for coupling the first and third decoders to the second decoder.
In U.S. Pat. No. 4,259,731 issued Mar. 31, 1981 to Moench, entitled QUIET ROW SELECTION CIRCUITRY, there is provided a quiet row select circuit for holding unselected word lines or row select lines in a memory array at a predetermined voltage potential. Transistors are used to couple each row select line to the predetermined voltage potential. The adjacent row select lines of at least one of the adjacent select lines is always coupled to the predetermined voltage when in an unselected state. A transistor is also used to couple each of the adjacent row select lines together and this transistor is enabled whenever the adjacent row select lines are non-selected so that both row select lines are coupled together to the predetermined voltage level.
In another reference of Moench, U.S. Pat. No. 4,200,917 issued Apr. 29, 1980, entitled QUIET COLUMN DECODER, a decoder is provided for semiconductor memory systems which prevents glitches from being coupled into the silicon substrate during the period of time that the sense amplifiers are sensing data on the bit sense lines. The quiet column decoder has double clock NOR gates which allows the address lines to be continuous nonmultiplexed lines. The double clocked NOR gate has two transistors for precharging a first and a second node within the NOR gate. Another transistor is coupled between the second node and a voltage reference terminal to serve as an enabling device for the NOR gate. The first node of the NOR gate serves as an output for the column decoder.
In U.S. Pat. No. 4,429,374 issued Jan. 31, 1984 to Tanimura, entitled MEMORY ARRAY ADDRESSING, an address decoder for one memory axis is disclosed which comprises NAND circuits while the address decoder for the other axis comprises NOR circuits. A semiconductor memory circuit device comprises at least first and second decoder circuits. The first decoder circuit is so constructed as to receive at least partial address signals among address signals of a plurality of bits and to provide decoded signals of the partial address signals as intermediate signals. The second decoder circuit is so constructed as to receive the intermediate signals, to thereby provide signals for selecting from among a plurality of memory circuits a memory circuit determined by the address signals of the plurality of bits.
A publication entitled "CMOS Decoder Circuit" by L. M. Terman, at page 2135 of Vol. 25, No. 4 September 1982 of the IBM Technical Disclosure Bulletin relates to improvements in CMOS decoder circuits, and particularly to a decoder circuit which does not dissipate DC power. The decoder is followed with two branches with CMOS drivers for word lines.
In Vol. 18, No. 12, May 1976 of the IBM Technical Disclosure Bulletin, G. H. Parikh in a publication entitled "High Speed FET Decoder" on page 3955 describes a field-effect transistor decoder circuit which allows improved speed of decoding FET random-access memories, by reducing the capacitance required to be discharged in an unselected decoder.
The speed is further increased by reducing the capacitance of the nodes to be discharged wherein isolation transistor devices are provided to isolate the capacitance on word-line voltage nodes to allow bootstrapping to occur if a node has not been discharged.
Other related prior art includes the following references:
U.S. Pat. No. 4,194,130 to Moench issued Mar. 18, 1980, entitled DIGITAL PREDECODING SYSTEM;
U.S. Pat. No. 4,433,257 to Kinoshita issued Feb. 21, 1984, entitled VOLTAGE SUPPLY FOR OPERATING A PLURALITY OF CHANGING TRANSISTORS IN A MANNER WHICH REDUCES MINORITY CARRIER DISRUPTION OF ADJACENT MEMORY CELLS;
U.S. Pat. No. 4,156,938 to Proebsting et al issued May 29, 1979, entitled MOSFET MEMORY CHIP WITH SINGLE DECODER AND BI-LEVEL INTERCONNECT LINES;
U.S. Pat. No. 4,344,005 to Stewart issued Aug. 10, 1982, entitled POWER GATED DECODING.